Prof. Dr.-Ing. Gökçe Aydos

  • accelerated computing on FPGAs
  • fault-tolerance for digital circuits
  • embedded systems
  • Publications

Professor

DEGG's 2.16

0991/3615-179


consulting time

by appointment


Zeitschriftenartikel
  • Gökçe Aydos
  • G. Fey
Empirical results on parity-based soft error detection with software-based retry, vol. 48, pg. 62-68.

In: Microprocessors and Microsystems

  • 2017

DOI: 10.1016/j.micpro.2016.09.009

Local triple modular redundancy (LTMR) is often the first choice to harden the FFs of a flash-based FPGA application against radiation-induced bitflips in space, but LTMR leads to an area overhead of roughly 300%. To cope with this significant overhead, we propose an error detection based approach. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from 29% up to 36% of the area overhead caused by LTMR.
  • Angewandte Informatik
  • DIGITAL
Hochschulschrift
  • Gökçe Aydos
Parity-based Error Detection with Recomputation for Fault-tolerant Spaceborne Computing
  • 2017
In radiation environment (e.g., space, nuclear reactor), electronics can fail due to bitflips in the flipflops of integrated circuits. A common solution is to triplicate the flipflops and connect their outputs to a voter. If one of the three bits is flipped, then the voter outputs the majority value and tolerates the error. This method is called triple modular redundancya (TMR). TMR can cause about 300% area redundancy. An alternative way is error detection with on-demand recomputation, where the recomputation is done by repeating the failed processing request to the processing circuit. The computation is done in consecutive transactions, which we call transaction-based processing. We implemented and evaluated the aforementioned alternative approach using parity checking on the Microsemi ProASIC3 FPGA, which is often used in space applications. The results show that parity-based error detection with our system recovery approach can save up to 54% of the area overhead that would be caused by the TMR, and achieve in most circuits slightly better timing results than TMR on ProASIC3. This area saving can be the key for fitting the application to a space-constrained chip.
  • Angewandte Informatik
  • DIGITAL
Beitrag (Sammelband oder Tagungsband)
  • Gökçe Aydos
  • G. Fey
Exploiting error detection latency for parity-based soft error detection, pg. 3-8.
  • 2016
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be the key for fitting the application onto the FPGA. A drawback of parity-based hardening is the significant impact on the critical path. To alleviate this error detection latency, pipeline structures in the design can be utilized. According to our results, this eliminates from 22% to 65% of the critical path overhead of the unpipelined error detection. Compared with LTMR, the new approach increases the critical path overhead of LTMR by a factor varying from 2 to 7.
  • Angewandte Informatik
  • DIGITAL
Beitrag (Sammelband oder Tagungsband)
  • Gökçe Aydos
  • G. Fey
In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR, pg. 272-274.

In: Formal Modeling and Verification of Cyber-Physical Systems. 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 (Advanced lectures by leading scientists on cyber-physical systems modeling and verification)

  • 2015
FPGAs are often utilized in space avionics. To protect the FPGA application data against radiation effects in space, data redundancy can be used. A well-known method is to triplicate the circuit and eliminate the erroneous circuit output with a local voter (TMR). Alternatively, in-circuit error detection with software-based error correction can be used, if the FPGA works as a co-module next to a processor running the mission software. In this work, we present an implementation of this method on a commonly used spacecraft data handling architecture.
  • Angewandte Informatik
  • DIGITAL
Beitrag (Sammelband oder Tagungsband)
  • Gökçe Aydos
  • G. Fey
Empirical results on parity-based soft error detection with software-based retry, pg. 1-4.
  • 2015

DOI: 10.1109/NORCHIP.2015.7364378

Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from 30 % up to 45 % of the area overhead caused by LTMR.
  • Angewandte Informatik
  • DIGITAL
Beitrag (Sammelband oder Tagungsband)
  • Gökçe Aydos
  • G. Fey
Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture, pg. 1415-1429.

In: Informatik 2015 - Informatik, Energie und Umwelt (28.09.-02.10.2015; Cottbus). null (GI-Edition : Proceedings)

  • 2015
  • Angewandte Informatik
  • DIGITAL

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Office location

Use the Degg's entrance at Veilchengasse 15-19 near the bike park. Walk up to the second floor and go through the non-glass door which will be open during office hours. Proceed to the room 2.16.